A new class of Edge Internet of Things (IoT) workloads is reshaping the traditional boundaries between microcontrollers (MCUs) and microprocessors (MPUs). These workloads combine always-on sensing and control with advanced artificial intelligence, rich multimedia processing, and responsive user experiences, all within strict power, thermal, and cost constraints. Purpose-built platforms now deliver the compute capacity, memory bandwidth, and media pipelines these applications require while retaining the energy efficiency and streamlined system design needed for battery-constrained, always-on form factors. For this emerging workload class, the traditional performance gap between MCUs and MPUs no longer defines the design choice.
The Synaptics Astra® SR200 series of xMCUs redefines Edge hardware by fusing low-power MCU heritage with microprocessor-grade multimodal processing. Building upon the foundational SR80 (focused on audio AI) and SR100 (focused on vision AI), the SR200 family combines audio, computer vision, rich display graphics, and transformer-ready neural acceleration into a unified, highly scalable microcontroller class.
The SR200 series enables self-hosted application stacks (such as smart camera engines, wearable GUIs, and interactive robotics) without requiring external coprocessors or active cooling. It integrates dual Arm Cortex compute cores, dedicated vision and audio ISPs, a 2.5D vector GPU, and up to 400 GOPS of Transformer-ready neural compute into a single energy-efficient System-in-Package.
Portfolio Structure and Scalable Product Lines
To address the diverse challenges that engineers face with commercial and industrial deployments, Synaptics structures the Astra SR200 series into three distinct, pin-to-pin compatible product lines: the SR210, SR230, and SR250. Every member of the product line is housed in an identical Flip-Chip Ball Grid Array (FCBGA) package layout, allowing system designers to establish a single hardware board schematic and scale processing capabilities up or down across product variants without redesigning physical printed circuit boards (PCBs).
| Feature / Specification | Astra SR210 | Astra SR230 | Astra SR250 |
|---|---|---|---|
| High-Performance Core | Arm Cortex-M85 @ 400 MHz (4 MB ILP SRAM) | Arm Cortex-M85 @ 600 MHz (5 MB ILP SRAM) | Arm Cortex-M85 @ 800 MHz (6 MB ILP SRAM) |
| High-Efficiency Core | Arm Cortex-M52 @ 100 MHz (1 MB ULP SRAM) | Arm Cortex-M52 @ 150 MHz (1.5 MB ULP SRAM) | Arm Cortex-M52 @ 200 MHz (2 MB ULP SRAM) |
| Torq™ NPU Performance | 200 GOPS | 300 GOPS | 400 GOPS |
| Target Subsystems | Always-on voice, single camera or single display | Vision + Display + AI, optional HiFi5 DSP | Dual Vision + Dual Display + Full Multimodal |
| Target Applications | Consumer sensor hubs, smart doorbells, thermostats | Mainstream smartwatches, smart sensors, cameras | Premium AR/VR glasses, robotics, industrial control |
This pin-to-pin scalability enables hardware reuse across product lines ranging from low-power activity trackers and smart thermostats to high-end smartwatches, smart doorbells, autonomous mobile robots (AMRs), and augment reality (AR) glasses. For example, a manufacturer can deploy the entry-level SR210 in a base consumer sensor hub, then seamlessly transition to the SR250 for a premium robotics controller by reusing the same base board architecture and much of the associated hardware and software infrastructure.[
This approach creates vertical and horizontal design scalability. With access to this broad portfolio of SKUs that are pin-to-pin compatible, designers, OEMs and ODMs can both scale up within a device class (from fitness tracker to watch) and scale across device categories (fitness trackers, watches, earbuds, glasses, and pendants).
Adaptive Power & Audio Wake-Up
Power optimization in the SR200 series is governed by a context-aware power management architecture partitioned into four fully independent power domains. This architecture features a tested, validated, ultra-low-power process node based on a continuous refinement strategy and approach for the segment, including IoT, edge AI, and wearable devices.
| Power Domain | Core & Hardware Subsystems | Memory Allocation | Primary Functional Responsibilities |
|---|---|---|---|
| Always-ON (AON) | Hardware VAD, PDM + FIFO, RTC, 8x GPIOs | Retention Buffers | Continuous audio listening, timekeeping, hardware wake events |
| Ultra-Low Power (ULP) | Arm Cortex-M52 (up to 200 MHz), 36x GPIOs | Up to 2 MB SRAM | Sensor fusion, wake-word detection, connectivity stacks |
| Low Power (LP) | HiFi5 DSP, Dual PDM, I2S, TDM, 80x GPIOs | Shared System SRAM | Multi-mic beamforming, acoustic ML, voice/audio playback |
| High Performance (HP) | Arm Cortex-M85 (up to 800 MHz), Torq NPU | Up to 6 MB SRAM | Burst AI inference, neural vision, 2.5D GPU display render |
The 3-Stage Audio Wake-Up Flow
A critical innovation in the SR200 power architecture is its hardware-enforced 3-stage audio wake-up flow, designed specifically for battery-operated devices that require wake-word listening, such as wearables and smart-home doorbells. The SR200 duty-cycles between low power states with millisecond precision:
- Stage 1: Always-ON (AON) Voice Activity Detection: The hardware Voice Activity Detector (VAD) listens continuously on incoming PDM microphone streams at microwatt power levels while the rest of the chip remains powered down.
- Stage 2: Ultra-Low Power (ULP) Keyword Verification: When human speech is detected, the AON domain wakes the efficiency-focused Arm Cortex-M52 core in the ULP domain after collecting approximately 10 milliseconds of audio data.
- Stage 3: Low Power (LP) Acoustic Processing & Intent Analysis: Once the wake-word is confirmed, the LP domain triggers the built-in DSP.
Multi-Die System-in-Package (SiP) and Custom DRAM Technology
To lower BOM cost and optimize device form factors to support an emerging class of systems (such as AI-enabled wearables), the Astra SR200 series incorporates an advanced multi-die System-in-Package (SiP) design[ANP3.1]. Within a single FCBGA package, Synaptics integrates three distinct silicon dies: a high-efficiency Compute Die, a Power Management IC (PMIC) die, and a massive High-Bandwidth Custom DRAM die.
Synaptics xMCUs push silicon boundaries by offering up to hundreds of megabytes of integrated custom DRAM operating across a wide 64-bit parallel bus. In the SR200 series, this memory interface delivers throughput up to 4 Gigabits per second (Gbps) directly inside the package, providing 7x lower access energy compared to external LPDDR2 memory and 3x lower power than LPDDR4x solutions.
| Memory Tier | Capacity & Technology | Bus Width / Bandwidth | Primary System Usage |
|---|---|---|---|
| Tier 1: LP On-Chip SRAM | Up to 6 MB SRAM | On-Die High-Speed Bus | Primary storage for High-Performance domain, NPU layer weights, display frame buffers |
| Tier 2: ULP Segmented SRAM | Up to 2 MB SRAM | Power-Segmented Bus | Sensor fusion buffers, connectivity stacks, always-on system state retention |
| Tier 3: Custom In-Package DRAM | Custom DRAM | 64-bit Bus @ up to 4 Gbps | Large AI neural model weights, high-resolution video frame buffers, self-hosted software stacks |
By integrating hundreds of megabytes of memory directly into the SiP, the SR200 series eliminates external DRAM footprints and board-level high-speed routing complexities. This self-contained memory architecture allows complex application stacks (such as real-time smartwatch GUIs and multi-camera computer vision engines) to run entirely self-hosted on the MCU without external memory chips.
Transformer-Ready Torq™ NPU & Open-Source Software Stack
At the core of the SR200’s artificial intelligence capabilities is the Torq™ NPU, co-developed in close collaboration with Google Research. Delivering up to 400 GOPS of neural performance, the Torq NPU is the first microcontroller-class neural processing unit featuring native bfloat16 (BF16) floating-point precision support alongside standard INT8 and INT16 quantization modes. Equipped with 256 Multiply-Accumulate (MAC) units, 256 KB of Local RAM (LRAM), and a RISC-V vector core, the Torq NPU is co-designed specifically to run both traditional Convolutional Neural Networks (CNNs) and modern Transformer architectures without re-spinning silicon.
Open Compiler Pipeline (MLIR / IREE) with Google Research Collaboration
To eliminate proprietary compiler lock-in and vendor fragmentation, Synaptics and Google Research co-developed an open-source compiler toolchain built upon MLIR (Multi-Level Intermediate Representation) and the IREE (Intermediate Representation Execution Environment) framework[ANP5.1][AS5.2]. Developers can train neural network models in PyTorch, ONNX, JAX, or TensorFlow Lite (LiteRT) and ingest them directly into the Torq compiler. The compiler lowers high-level AI dialects (Torch-mlir, StableHLO, TOSA) into computational dialects (Linalg, Tensor, Math) and targets optimized bytecode output that executes seamlessly across the Torq AI engine with the Coral NPU, GPU, or host CPUs.
Mainline Open-Source RTOS Leadership
Software deployment is centered around upstream, mainline Zephyr RTOS and FreeRTOS integration. Synaptics actively upstreaming SR200 device drivers and Board Support Packages (BSPs) directly into mainline Zephyr repositories ensures long-term open-source software maintainability, standard toolchain compatibility (GCC, LLVM), and rapid community software adoption.
Multimodal Hardware Subsystems: Dual Vision Pipelines, Graphics, & Audio
The SR200 series integrates specialized hardware blocks dedicated to vision processing, graphics rendering, and multichannel audio, enabling true end-to-end multimodal perception on a single chip.
Dual Image Signal Processors (ISPs)
A new development in [ANP6.1]the SR200 vision architecture is the inclusion of two independent, coexisting Image Signal Processors (ISPs) tailored for fundamentally different visual workloads:
| ISP IP Block | Target Domain & Max Resolution | Silicon & Power Footprint | Primary Workloads & Applications |
|---|---|---|---|
| ISP Lite (Machine Vision) | Optimized for CV, up to 2 MP | Ultra-low power & minimal silicon footprint | Presence detection, gesture recognition, neural object classification, sensor fusion |
| ISP Full (Human Perception) | Optimized for Photography, up to 8 MP | High-performance scaling & color processing | Full-resolution video recording, high-quality photography, smart doorbell streams |
Supported by dual MIPI CSI camera receiver ports, the dual vision pipeline allows low-resolution machine vision tracking to run continuously through ISP Lite while ISP Full remains powered off, waking the full 8 MP imaging pipeline only when high-quality video capture or human viewing is required.
Graphics, Display Drivers, and AR Glasses Support
For visual feedback, the SR200 features dual MIPI DSI display drivers coupled with a hardware-accelerated 2.5D vector GPU. This dual-display architecture supports three distinct smart glass display configurations on a single silicon platform:
- No-Display Audio/Vision Glasses: Operates purely via camera capture, audio I/O, and NPU inference (similar to smart audio/camera glasses).
- Monocular Display Glasses: Drives a single display engine positioned on one lens for heads-up notifications and simple AR overlays.
- Binocular Display Glasses: Drives independent left and right MIPI DSI display streams simultaneously for immersive 3D AR stereo visual experiences.
High-Fidelity Audio Subsystem
The audio subsystem centers around the DSP integrated within the Low Power domain. Accommodating multiple audio interfaces—including ULP PDM (1 port), LP PDM (2 ports), I2S (2 ports), and TDM (2 ports)—the SR200 supports 2-to-6 microphone arrays alongside 2 speaker channels, enabling advanced multi-microphone beamforming, acoustic echo cancellation, and acoustic event detection.
Industrial & Consumer High-Speed Connectivity
Beyond consumer wearables, the Astra SR200 series is engineered for industrial automation, factory vision and robotics. Industrial SKUs incorporate time-deterministic networking interfaces to support real-time synchronization across distributed control nodes.
| Interface Category | Supported Protocols & Hardware Instantiations | Industrial & System Application |
|---|---|---|
| Time-Sensitive High Speed | 1 Gigabit Ethernet with IEEE 1588 TSN | Real-time clock-synchronized industrial automation, AMR control, factory line vision |
| Industrial Bus | 2x CAN-FD (Flexible Data-Rate) | Robotics sensor buses, automotive submodules, industrial controller networks |
| Storage Interfaces | Octal SPI (xOSPI) @ DDR 200MHz (XIP), Dual QSPI, SDIO/eMMC @ 200MHz | Fast flash boot, execute-in-place (XIP) memory expansion, high-speed log storage |
| Serial & System I/O | USB 2.0 HS, 6x UART, 6x SPI, 6x I2C, 2x I3C, 12x PWM, 124x total GPIOs | Debugging, external wireless modules, sensor connections, motor drive control |
Hardware-Rooted Silicon Security
Security in the Astra SR200 series is integrated natively into the physical silicon rather than bolted on through software layers. All cryptographic operations, key management, and security attestation are isolated within a dedicated hardware security subsystem.
- PSA Level 3 Certified: Architected to meet Arm Platform Security Architecture (PSA) Level 3 requirements, guarding against sophisticated hardware and physical side-channel attacks.
- Common Criteria CC EAL4+ Certified: Evaluated under international Common Criteria standards for high-assurance commercial security deployments.
- Digital Anti-Tamper Sensors: Monitors physical chip parameters (voltage, temperature, clock frequency, laser glitching) and triggers immediate zeroization of sensitive key material upon physical intrusion detection.
- Secure OTP & Hardware Root of Trust: Features One-Time Programmable (OTP) memory for hardware-rooted secure boot, cryptographic device identity certificates, and debug access control locks.
Bridging the Edge AI Divide
The Synaptics Astra SR200 Series redefines edge silicon by closing the historical performance gap between traditional microcontrollers and Linux-class microprocessors. By uniting high-performance compute, a Transformer-ready NPU with native bfloat16 support, a four-domain adaptive power architecture, and custom high-bandwidth SiP DRAM, Synaptics provides a single platform capable of self-hosted multimodal processing.
Whether deployed in battery-constrained wearables, smart home devices, or real-time industrial robotics, the SR210, SR230, and SR250 offer pin-to-pin compatible hardware scalability that protects design investments across product lines. Backed by mainline Zephyr RTOS integration, an open MLIR/IREE compiler pipeline, and PSA Level 3 silicon security, the Astra SR200 family equips engineering teams to deploy physical AI at scale without compromising power, security, or developer independence.
Accelerate Your Edge AI Roadmap
Ready to transform your Edge and wearable devices with multimodal AI?
Explore the Product Portfolio: Compare the pin-compatible Astra SR210, SR230, and SR250 microcontrollers to identify the compute, vision, and power profile for your application.
Leverage the Open Ecosystem: Integrate mainline Zephyr RTOS drivers and utilize the open-source Torq compiler pipeline co-developed with Google Research.
Partner with Synaptics: Visit www.synaptics.com to request evaluation hardware, access technical documentation, and collaborate directly with product teams to kickstart your deployment.